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a the powerpc a a 440 core a high-performance, superscalar processor core for embedded applications ibm microelectronics division research triangle park, nc 09/21/1999
powerpc 440 core page 2 of 18 09/21/1999 overview the powerpc 440 cpu core is the latest addition to ibm?s family of 32-bit risc powerpc embedded processor cores. the ppc440?s high-speed, superscalar design and book e enhanced powerpc architecture ? put it at the leading edge for high performance system-on-a-chip (soc) designs. the ppc440 core marries the performance and features of standalone microprocessors with the flexibility, low power, and modularity of embedded cpu cores. target applications the ppc440 core is primarily designed for applications in which maximum performance and extensive peripheral integration are the critical selection criteria. target market segments for the ppc440 core include: consumer applications including digital cameras, video games, set-top boxes, and internet appliances office automation products such as laser printers, thin-client systems, and sub-notebooks storage and networking products such as raid controllers, routers, atm switches, cellular basestations, and network cards features 2-way superscalar design out-of-order issue, execution, and completion dynamic branch prediction single-cycle branch latency three execution pipelines single-cycle throughput on 32x32 multiply 24 dsp operations (16x16+32->32, mac with single-cycle throughput) real-time non-invasive instruction trace typical application a typical system on a chip design with the ppc440 core uses the coreconnect tm bus structure for system level communication. high bandwidth peripherals and the ppc440 core communicate with one another over the processor local bus (plb). less demanding peripherals share the on-chip peripheral bus (opb) and communicate to the plb through the opb bridge. the plb and opb provide common interfaces for peripherals and enable quick turnaround, custom solutions for high volume applications. figure 1 shows an example ppc440 core-based system on a chip, illustrating the two-level bus structure and modular core-based design.
powerpc 440 core page 3 of 18 09/21/1999 figure 1 . example ppc440 core + asic specifications performance (dhrystone 2.1) 1000 mips @ 555mhz (est.), nominal silicon, 1.8v, 55 c 720 mips @ 400mhz (est.), slow silicon, 1.65v, 85 c frequency 0 ? 400mhz , slow silicon, 1.65v, 85 c 555mhz nominal power dissipation 2.5mw / mhz @ 1.8v (est.), hard core with 32ki / 32kd caches architecture 32-bit powerpc book e compliant, application code compatible with all powerpc processors die size 4.0 mm 2 for cpu only (est.) caches 0-64kb, 32-way to 128-way associative technology 0.18 m cmos copper technology 0.12 m l eff , 4 levels of metal power supply 1.8 volts transistors 5.5m, hard core with 32ki / 32kd caches operating range -40 c to 125 c, 1.6v to 1.9v data bandwidth up to 6.4 gb/sec via three 128-bit, 200mhz coreconnect bus interfaces table 1 - 440 cpu core specifications embedded design support the ppc440 core, as a member of the powerpc 400 family, is supported by the ibm powerpc embedded tools tm program, in which over 80 third party vendors have combined with ibm to provide a complete tools solution. development tools for the ppc440 include c/c++ compilers, debuggers, bus functional models, hardware/software co-simulation environments, and real-time operating systems. as part of the tools program, ibm maintains a complete set of development tools by offering the high c/c++ compiler, riscwatch tm debugger with risctrace tm trace interface, vhdl and verilog simulation models and a ppc440 core superstructure development kit.
powerpc 440 core page 4 of 18 09/21/1999 ppc440 cpu core organization ppc440 cpu the ppc440 cpu operates on instructions in a dual issue, seven stage pipeline, capable of dispatching two instructions per clock to multiple execution units and to optional auxiliary processor units ( apus). the ppc440 core is shown in figure 2 . figure 2 - ppc440 core block diagram the pipeline contains the following stages, as shown in figure 3 : 1. ifth ? fetch instructions from instruction cache 2. pdcd ? pre-decode; partial instruction decode 3. diss ? decode/issue; final decode and issue to units 4. racc ? register access; read from multi-ported general purpose register (gpr) file 5. exe1/agen ? execute stage 1; complete simple arithmetics, generate load/store address 6. exe2/crd ? execute stage 2; multiplex in results from units in preparation for writing into gpr file, data cache access 7. wb ? writeback; write results into gpr file from integer operation or load operation
powerpc 440 core page 5 of 18 09/21/1999 figure 3 - ppc440 cpu pipeline instruction fetch and pre-decode during the instruction fetch stage (ifth), an entire cache line (eight words) is read into the instruction cache line read buffer. from there, the next two instructions in the pre-decode buffers pdcd0 and pdcd1 during the pdcd stage. the instruction cache is virtually indexed and tagged, and translation is performed in parallel with the cache access. branch unit the ppc440 uses a branch history table (bht) to maintain dynamic branch prediction of conditional branches. to perform dynamic branch prediction, a 2-bit counter in the bht is used to decide whether prediction should agree or disagree with the normal powerpc static branch prediction. the counter counts up if branch determination agrees, and down if it disagrees. once the counter saturates, it can only count away from saturation. therefore, four valid states exist: ?strongly agree?, ?agree?, ?disagree?, and ?strongly disagree?. by agreeing or disagreeing with static branch prediction, different branches can use the same counter in the bht and have opposite static predictions, without the machine necessarily mispredicting a branch. the branch target address cache (btac) is used to predict branches and deliver their target addresses before the instruction cache can deliver the same data. it is accessed during ifth, whereas normal branch prediction would not occur until pdcd, and therefore avoids a one cycle penalty. the btac is made up of an odd and even btac containing eight entries each. only unconditional branches and bdnz
powerpc 440 core page 6 of 18 09/21/1999 instructions are stored, which gives a significant performance boost while keeping the design straightforward. decode and issue the four-entry decode queue accepts up to two instructions per clock submitted from the pre-decode buffers. instructions always enter the lowest empty or emptying queue position, behind any instructions already in the queue. therefore, the queue fills from the bottom up, instructions stay in order, and no bubbles exist in the queue. a significant portion of decode is performed in the lowest two positions (diss0 and diss1). up to two instructions exit the queue based on the instructions? decode and pipeline availability, and are issued to the racc stage. diss1 can issue out of order with respect to diss0. register access conceptually, the gpr file consists of thirty-two, 32-bit general purpose registers. it is implemented as two 6-port arrays, (one array for lracc, one for iracc) each with thirty-two, 32-bit registers containing three write ports and three read ports. on all gpr updating instructions, the appropriate gpr write ports will be written in order to keep the contents of the files the same. on gpr reads, however, the gpr read ports are dedicated to instructions that are dispatched to a racc?s associated pipe(s). execution pipelines the ppc440 contains three execution pipes: a load/store pipe (?l-pipe?), a simple integer pipe (?j-pipe?), and a complex integer pipe (?i-pipe?). the l-pipe and j-pipe instructions are dispatched from the lracc; i-pipe instructions are dispatched from iracc. the three pipes together perform all 32-bit powerpc integer instructions in hardware compliant with the powerpc book e specification. table 2 lists the rules for dispatching to each of the three execution pipes. l-pipe only loads/stores 1 , cache instructions, mbar, msync i-pipe or j- pipe 2 add, addi, addis, and, andc, cntlzw, eqv, extsb, extsh, nand, neg, nor, or, orc, ori, oris, xori, xoris, rlwimi, rlwinm, rlwnm, slw, srw, subf i-pipe only branches, multiplies, divides, move to/from dcr/spr, indirect xer updates, indirect lr/ctr updates, indirect cr updates, cr-logicals, mac instructions, mcrf, mcrxr, mtcrf, mfcr, compares, dlmzb, isync, rfi, rfci, sc, wrtee, wrteei, mtmsr, mfmsr, traps table 2 ? rules for instruction issue the mac unit is an auxiliary processor unit (apu) which adds 24 operations to the ppc440 instruction set. mac instructions operate on either signed or unsigned 16 bit operands and accumulate the results in a 32-bit gpr. all mac unit instructions have single cycle throughput. the mac unit is contained within the i-pipe. 1 the stwcx. instruction goes down both the l-pipe as well as the i-pipe, in order to update the cr. 2 instructions which update the cr or xer are not issued to the j-pipe.
powerpc 440 core page 7 of 18 09/21/1999 instruction and data caches processor local bus (plb) memory access the ppc440 has three independent 128-bit processor local bus (plb) master interfaces, one for instruction fetches, one for data reads, and a third for data writes. memory accesses are performed through the plb interfaces to/from the instruction cache (i-cache) or data cache (d-cache) units. having three independent bus interfaces for the cache units provides maximum flexibility for designs to optimize system throughput. memory accesses (loads/stores) which hit in the cache achieve single-cycle throughput. cache configuration the ppc440 has separate instruction and data caches with 8 word (32 byte) cache lines. instruction and data cache sizes are factory-configurable to any combination of 0kb, 8kb, 16kb, 32kb, or 64kb cache sizes. configurable cache sizes provide designers with a parameter for optimizing the ppc440 to a desired price-performance for a particular application. the caches are highly associative, with associativity varying with cache size as shown in table 3 . high associativity enables advanced cache functions such as locking and transient memory regions (see ?cache partitioning? below). cache size ways 8 kb 32 16kb 64 32kb 64 64kb 128 table 3 ? number of ways for different ppc440 cache sizes the cache arrays are non-blocking. non-blocking caches allow the ppc440 to overlap execution of load/store instructions while instruction fetches take place over the plb. the caches, therefore, continue supplying data and instructions without interruption to the pipeline. the ppc440 replaces cache lines according to a round-robin replacement policy. the initial ppc440a4 core offering will include a 32kb instruction cache and 32kb data cache. these caches are physically constructed using two, 16kb camram macros, each consisting of 8, 2kb sub- banks (or ?sets?). this organization facilities low-power operation and fast hit/miss determination. cache partitioning the ppc440 caches have the ability to be separated into ?normal?, ?transient?, and ?locked? regions. normal regions are what is traditionally thought of regarding cache replacement. transient regions are used for data that is used temporarily and then not needed again, such as the data in a particular jpeg image. a separate transient region avoids castouts of more commonly accessed code in the normal region. the locked region is for code that is not to be cast out of the cache, and is the resulting region not included in the normal and transient regions. the regions are set via ?victim? ceiling and floor pointers, as shown in figure 4 . figure 4 shows two examples of cache partitioning, the left side shows separate transient and normal regions, and the right side shows part of the normal region overlapping with the transient region. the normal ceiling is defined as the top of the cache.
powerpc 440 core page 8 of 18 09/21/1999 figure 4 ? two examples of cache partitioning i-cache speculative pre-fetching the i-cache utilizes a programmable speculative pre-fetch mechanism to enhance performance. software can enable up to three additional lines to be speculatively pre-fetched, using a burst protocol, upon any instruction cache miss. when this mode is enabled, the i-cache controller will automatically inspect the i- cache on a miss to see if any of up to the next three lines are also misses. if so, the hardware will present a burst request to the plb immediately after the original line fill request. this speculative burst request takes advantage of the throughput capability of standard memory architectures such as sdram and brings in anticipated subsequent instructions after a miss. furthermore, if the instruction stream branches away from the lines which are being speculatively filled, the burst request which is filling the speculative lines can be abandoned in the middle, and a new fill request at the branch target location immediately initiated. there is a programmable "threshold" to determine when to abandon a speculative line fill that may have been in progress at the time of a branch redirection. this threshold designates how many doublewords of the speculative cache line must be received to not abandon a current line fill. in this fashion, the speculative pre-fetch mechanism can be carefully tailored to provide optimum performance for specific applications and memory subsystems. d-cache line fills the d-cache contains three line fill buffers and can queue up to four load misses to three separate cache lines. the ppc440 will then execute past these load misses, until the queue is full or the pipes are held waiting for a load value. the d-cache controller places the target word on the bypass path as the fill buffer captures data words off the plb. additional requests of the cache line held in the fill buffer are also forwarded directly to the operand registers in the execute unit. d-cache non-cacheable store gathering the d-cache ?gathers? up to 16 bytes for non-cacheable, write-through, and w/o allocate stores, and will burst the quadword to the plb for fast writes to non-cacheable memory. d-cache write-back and write-through modes the d-cache supports write-back or write-through mode. in write-back mode, store hits are written to the cache and not to main memory. main memory is later modified if and when the line is flushed from the cache. in write-through mode, the data cache controller writes main memory for store misses as well as
powerpc 440 core page 9 of 18 09/21/1999 store hits ; every store operation generates a plb write request. (although write-through requests to non- cacheable memory can be gathered as previously mentioned). d-cache store allocation the d-cache can be programmed whether or not to allocate a line on a d-cache store miss. write-on- allocate is enabled by default. in this mode, a store miss to cacheable memory forces the data cache controller to allocate a line in the data cache and generate a line fill. in contrast, when ?without allocate? is enabled, a store miss to cacheable memory will not allocate a line data cache and will simply write the data to memory. big endian and little endian support the ppc440 supports big endian or little endian byte ordering for instructions and data stored in external memory. the powerpc book e architecture is endian neutral ; each page in memory can be configured for big or little endian byte ordering via a storage attribute contained in the tlb entry for that region. strapping signals on the ppc440 core initialize the beginning tlb entry?s endian attribute, so the ppc440 can boot from little or big endian memory.
powerpc 440 core page 10 of 18 09/21/1999 memory management unit (mmu) the mmu supports multiple page sizes as well as a variety of storage protection attributes and access control options. multiple page sizes improve tlb efficiency and minimize the number of tlb misses. the ppc440 gives programmers the flexibility to have any combination of the following eight possible page sizes in the translation look-aside buffer (tlb) simultaneously: 1kb, 4kb, 16kb, 64kb, 256kb, 1mb, 16mb and 256mb. having an extremely large page size allows users to define system memory with a minimal number of tlb entries, thereby simplifying tlb allocation and replacement. small page sizes prevent the wasting of memory when allocating small areas of data. each page of memory is accompanied by a set of storage attributes. these attributes include cacheability, write through/write back mode, big/little endian, guarded and four user-defined attributes. the user- defined attributes can be used to mark a memory page with an application-specific meaning. the guarded attribute controls speculative accesses. the big/little endian attribute marks a memory page as having big or little endian byte ordering. write through/write back specifies whether memory is updated in addition to the cache during store operations. two of the user-defined storage attributes can be programmed for special functions inside the core. one can be enabled to designate normal or transient cache regions. another can be enabled to control whether or not store misses allocate a line in the d-cache. access control bits in the tlb entries enable system software to control read, write, and execute access for programs in both user and supervisor states. the mmu includes a 64-entry fully-associative unified tlb to reduce the overhead of address translation. contention for the main tlb between data address and instruction address translation is minimized through the use of a four-entry instruction shadow tlb (itlb) and an eight-entry data shadow tlb (dtlb). the itlb and dtlb shadow the most recently used entries in the unified tlb. the mmu manages the replacement strategy of the itlb and dtlb leaving the unified tlb to software control. real-time operating systems are free to implement their own replacement algorithm for the unified tlb.
powerpc 440 core page 11 of 18 09/21/1999 interrupt handling logic the ppc440 services exceptions generated by error conditions, the internal timer facilities, debug events, and the external interrupt controller (eic) interface. altogether, there are sixteen different interrupt types supported. interrupts are divided into two classes, critical and non-critical. each class of interrupt has its own pair of save/restore registers for holding the program counter and machine state. separate save/restore registers allow the ppc440 to quickly handle critical interrupts even within a non-critical interrupt handler. when an interrupt is taken, the ppc440 automatically writes the program counter and machine state to save/restore register srr0 and srr1 respectively for non-critical interrupts, or csrr0 and csrr1 respectively for critical interrupts. the machine status and program counter are automatically restored at the end of an exception handler when the return from interrupt (rfi) or return from critical interrupt (rfci) instruction is executed.
powerpc 440 core page 12 of 18 09/21/1999 timers the ppc440 contains a 64-bit time base and three timers: the decrementer (dec), the fixed interval timer (fit), and the watchdog timer (wdt). the time base counter increments synchronously with the cpu clock or an external clock source. the three timers are synchronous with the time base. the dec is a 32-bit register that decrements at the time base increment rate. the user loads the dec register with a value to create the desired delay. when the register reaches zero, the timer stops decrementing and generates a decrementer interrupt. optionally, the dec can be programmed to auto- reload the value last written to the dec auto-reload register, after which the dec continues to decrement. the fit generates periodic interrupts based on one of four selectable bits in the time base. when the selected bit changes from 0 to 1, the ppc440 generates a fit exception. the watchdog timer provides a periodic critical-class interrupt based on a selected bit in the time base. this interrupt can be used for system error recovery in the event of software or system lockups. users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an intervening clear from software. if enabled, the watchdog timer generates a reset unless an exception handler updates the watchdog timer status bit before the timer has completed two of the selected timer intervals.
powerpc 440 core page 13 of 18 09/21/1999 debug logic all architected resources on the ppc440 can be accessed through the debug logic. upon a debug event, the ppc440 provides debug information to an external debug tool. three different types of tools are supported depending on the debug mode: rom monitors, jtag debuggers and instruction trace tools. internal debug mode in internal debug mode, a debug event enables exception-handling software at a dedicated interrupt vector to take over the ppc440 and communicate with a debug tool. exception-handling software has read-write access to all registers and can set hardware or software breakpoints. rom monitors typically use the internal debug mode. external debug mode in external debug mode, the ppc440 enters stop state (i.e., stops instruction execution) when a debug event occurs. this mode offers a debug tool non-invasive read-write access to all registers in the ppc440 via the jtag interface. once the ppc440 is in stop state, the debug tool can start the ppc440, step an instruction, freeze the timers or set hardware or software break points. in addition to ppc440 control, the debug logic is capable of writing instructions into the instruction cache, eliminating the need for external memory during initial board bring up. debug wait mode debug wait mode offers the same functionality as external debug mode with one difference; in debug wait mode, the ppc440 will respond to interrupts and temporarily leave stop state to service them before returning to debug wait mode. in external debug mode, by contrast, interrupts are disabled while in stop state. debug wait mode is particularly useful when debugging real-time control systems. real-time trace debug mode in real-time trace debug mode, instruction trace information is continuously broadcast to the trace port. when a debug event occurs, an external debug tool saves instruction trace information before and after the event. the number of traced instructions depends only on the memory buffer depth of the trace tool. debug events debug events signal the debug logic to either stop the ppc440, put the ppc440 in debug wait state, cause a debug exception, or save instruction trace information, depending on the debug mode. table 4 on the following page lists the possible debug events and their description.
powerpc 440 core page 14 of 18 09/21/1999 debug event description branch taken a branch taken debug event occurs prior to the execution of a taken branch instruction. instruction completion the instruction completion debug event occurs after the completion of any instruction. return from interrupt the return from interrupt debug event occurs after the completion of an rfi or rfci instruction. interrupt the interrupt debug event occurs after an interrupt is taken. trap the trap debug event occurs prior to the execution of a trap instruction, where the trap condition is met. instruction address compare (iac) the iac debug event occurs prior to the execution of an instruction at an address that matches the contents of one of four iac registers (iac1, iac2, iac3, and iac4). alternatively, the registers can be combined to cause an iac debug event prior to the execution of an instruction at an address contained in one of the following ranges as specified by the four iac registers: iac1 <= range < iac2 (inclusive), iac3 <= range < iac4 (inclusive), range low < iac1 < iac2 <= range high (exclusive), or range low < iac3 < iac4 <= range high (exclusive). data address compare (dac) the dac debug event occurs prior to the execution of an instruction that accesses a data address matching the contents of one of the two dac registers (dac1 and dac2). alternatively, the registers can be combined to cause a dac debug event occurs prior to the execution of an instruction that accesses a data address within one of the following ranges specified by the two dac registers: dac1 <= range < dac2 (inclusive), or range low < dac1 < dac2 <= range high (exclusive). data value compare (dvc) the data value compare debug event occurs prior to the execution of an instruction that accesses a data address matching one of the two dac registers (or within a dac range) and containing a particular data value as specified by one of the two dvc registers. the dvc debug event may occur when a selected data byte, half-word or word matches the corresponding element in dvc1 or dvc2. unconditional event an unconditional debug event is set by a debug tool through the jtag port or by asic logic external to the ppc440. table 4 - debug events
powerpc 440 core page 15 of 18 09/21/1999 power management the ppc440 core, in keeping with the ibm powerpc 400 family tradition, utilizes aggressive power management techniques for minimizing power. the ppc440 utilizes three key techniques: redundant operand registers, half-cycle latch stabilization, and dynamic clock gating. redundant operand registers redundant operand registers are used at various pipeline stages for feeding operands to each of the execution units. this saves power by preventing unused units from seeing the operand values being used by other units and improves performance by reducing loading and wire length in critical stages. half-cycle latch stabilization half-cycle stabilization latches minimize the propagation of glitches to downstream logic. this is easily employed since the ppc440 core contains a master/slave latch arrangement for scan-test purposes. therefore, a master-only latch is simply needed in the logic path that is switching in the first half of a cycle. for example, if the select lines for a mux are being determined in the first half of a cycle, then by putting a master-only latch on these select lines before delivering them to the mux, the mux outputs are prevented from glitching while the select lines are being determined. conversely, if the data lines are unstable in the first half of a cycle, a stabilization latch may be used on the data inputs, while leaving the select lines alone. dynamic clock gating the most important feature of the ppc440?s dynamic power management is the extensive use of clock gating. given the ppc440?s master/slave latch organization, there are two possible gates that can be used. the relationship between them, and their relative affect on the clock splitter and hence power are shown in figure 5 . figure 5 - ppc440 clock gating in this figure, the early gate blocks the phase 1 clock and prevents the master latch from loading, while the late gate blocks the phase 2 clock and prevents the slave latch from loading. as illustrated in the simplified block diagram of the clock splitter, the early gate must arrive by mid-cycle -- which is when the system clock falls. if the gate is activated by this point, then the net effect is that internal to the clock splitter the fall on the system clock is never observed, and both the phase 1 and the phase 2 clock splitter
powerpc 440 core page 16 of 18 09/21/1999 outputs remain stable, preventing any downstream master latches from loading, and hence their associated slave latches will not change either. this affords the maximum power savings, with the downstream logic dissipating no power other than leakage, and the clock splitter itself using almost zero power. in the event that the gate for a given latch cannot be determined by mid-cycle, the late gate can be used, which does not prevent the system clock fall and consequent phase 1 clock rise, but does prevent the corresponding next phase 2 clock rise. this does not save as much power, but the timing is much more relaxed and the power savings are still considerable.
powerpc 440 core page 17 of 18 09/21/1999 core external interfaces processor local bus (plb) interface the ppc440 accesses system resources through three independent plb interfaces: one for instruction fetches, one for data reads, and a third for data writes. each plb controller is a 128-bit plb master. the plb is the high performance coreconnect bus optimized for soc design. dcr bus interface the device control register (dcr) bus is a configuration bus for components external to the ppc440. using the dcr bus to manage status and configuration registers reduces plb traffic and improves system bandwidth and integrity. system resources on the dcr bus are protected or isolated from wayward code since the dcr bus is not part of the system memory map. auxiliary processor unit (apu) interface the apu interface enables a custom design implementation to tightly couple coprocessor-type macros to the ppc440. the apu interface provides sufficient functionality to attach macros such as a full powerpc floating point unit (single or double precision), a multimedia macro, dsp, or other custom functions implementing algorithms appropriate for the system application. the apu interface supports dual-issue pipeline designs, and utilizes a full 128-bit load/store path to the d-cache. the interface can be used with macros that contain their own register files, or with simpler macros which use the cpu?s register file for source and/or target operands. the apu interface provides customers the capability to execute instructions that are not part of the powerpc book e architecture concurrently with the ppc440. accordingly, areas have been reserved within the architected instruction space to allow for customer- or application-specific extensions. external interrupt controller (eic) interface the eic interface extends interrupt support to logic external to the ppc440 through the external and critical interrupt signals. these inputs are level sensitive. the critical interrupt and external interrupt signals are conceptually logic or?s of all implementation-specific critical and non-critical interrupts outside the core. debug interface debugging interfaces on the ppc440, consisting of the jtag and instruction trace ports, offer access to resources internal to the core and assist in software development. the jtag port provides the ability for external debug tools to gain control of the processor for debug purposes. this interface provides debuggers such as riscwatch with processor control that includes stepping, stopping, and starting the ppc440. the trace port furnishes programmers with a mechanism for acquiring instruction traces. this trace information is captured via an external trace tool, such as risctrace. the ppc440 is capable of tracing before, around, or after an occurring debug event.
powerpc 440 core page 18 of 18 09/21/1999 for further information regarding the powerpc 440 core, contact an ibm microelectronics sales representative. to identify your local sales representative, view the listing on the www at: http://www.chips.ibm.com/support/ ? international business machines corporation, 1999 all rights reserved ibm, the ibm logo, coreconnect, powerpc, the powerpc logo, powerpc architecture, powerpc embedded tools, risctrace and riscwatch are trademarks of international business machines corporation. other company, product, and service names may be trademarks or service marks of others. ibm will continue to enhance products and services as new technologies emerge. therefore, ibm reserves the right to make changes to its products, other product information, and this publication without prior notice. please contact your local ibm microelectronics representative on specific standard configurations and options. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. no warranties of any kind, including but not limited to the implied warranties of merchantability or fitness for a particular purpose are offered in this document.

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